Dual-loop DPLL gear-shifting algorithm for fast synchronization

DOI10.1109/82.598428MaRDI QIDQ4372818zbMATH OpenOpenAlexFDO

Authors Beomsup Kim

Publication date 28 August 2000

Published in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/82.598428

Mathematics Subject Classification ID

Communication theory (94A05)

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