Efficient constant coefficient multiplication using advanced FPGA architectures

DOI10.1007/3-540-44687-7_57MaRDI QIDQ4787319zbMATH OpenFDO

Authors Michael J. Wirthlin, Brian McMurtrey

Publication date 6 January 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/3-540-44687-7_57

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computing methodologies and applications (68U99)

Recommendations

• Multiple constant multiplication optimizations for field programmable gate arrays. With a preface by Prof. Dr.-Ing. Peter Zipf
• Dynamic constant coefficient convolvers implemented in FPGAs
• Efficient realization of large size two's complement multipliers using embedded blocks in FPGAs
• Run-time-reconfigurable multi-precision floating-point matrix multiplier intellectual property core on FPGA
• A digit-serial structure for reconfigurable multipliers

Cited in

(3)

• A HDL generator for flexible and efficient finite-field multipliers on FPGAs
• Multiple constant multiplication optimizations for field programmable gate arrays. With a preface by Prof. Dr.-Ing. Peter Zipf
• Efficient hardware multiplicative inverters

This page was built for publication: Efficient constant coefficient multiplication using advanced FPGA architectures

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4787319)