Efficient memory management for high-speed ATM systems

DOI10.1023/A:1011250815826MaRDI QIDQ5944331zbMATH OpenOpenAlexWikidataFDO

Authors Dimitrios N. Serpanos, P. Karakonstantis

Publication date 19 November 2001

Published in Design Automation for Embedded Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1011250815826

zbMATH Keywords

ATM systemshigh-speed queue manager

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Computing methodologies and applications (68U99)

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Cited in

(1)

• Buffering high-speed packets with tri-stage memory array and its performance analysis

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