Mathematical Research Data Initiative
Main page
Recent changes
Random page
SPARQL
MaRDI@GitHub
New item
In other projects
MaRDI portal item
Discussion
View source
View history
English
Log in

Buffering high-speed packets with tri-stage memory array and its performance analysis

From MaRDI portal
Publication:3365698
Jump to:navigation, search

zbMATH Open1083.68529MaRDI QIDQ3365698FDOQ3365698


Authors: Peng Wang, Peng Yi, Depeng Jin, Lieguang Zeng Edit this on Wikidata


Publication date: 23 January 2006





Recommendations

  • scientific article; zbMATH DE number 2080898
  • Optimum Scheduling and Memory Management in Input Queued Switches With Finite Buffer Space
  • High-performance switching based on buffered crossbar fabrics
  • Modèles Analytiques de Routeurs
  • Efficient memory management for high-speed ATM systems


zbMATH Keywords

packet buffer


Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)



Cited In (2)

  • Analysis of the input to a buffer storage in front of a packet switch
  • Efficient memory management for high-speed ATM systems





This page was built for publication: Buffering high-speed packets with tri-stage memory array and its performance analysis

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3365698)

Retrieved from "https://portal.mardi4nfdi.de/w/index.php?title=Publication:3365698&oldid=16629249"
Tools
What links here
Related changes
Printable version
Permanent link
Page information
This page was last edited on 4 February 2024, at 15:30. Warning: Page may not contain recent updates.
Privacy policy
About MaRDI portal
Disclaimers
Imprint
Powered by MediaWiki