Faster pairing coprocessor architecture

DOI10.1007/978-3-642-36334-4_10MaRDI QIDQ4912494zbMATH OpenOpenAlexFDO

Authors Gavin Xiaoxu Yao, Junfeng Fan, Ray C. C. Cheung, Ingrid Verbauwhede

Publication date 4 April 2013

Published in Pairing-Based Cryptography – Pairing 2012 (Search for Journal in Brave)

Full work available at URL https://lirias.kuleuven.be/handle/123456789/349573

zbMATH Keywords

field programmable gate array (FPGA)optimal pairingresidue number system (RNS)

Mathematics Subject Classification ID

Applications to coding theory and cryptography of arithmetic geometry (14G50) Mathematical problems of computer architecture (68M07) Cryptography (94A60)

Recommendations

• FPGA implementation of pairings using residue number system and lazy reduction
• Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform
• High speed flexible pairing cryptoprocessor on FPGA platform
• RNS arithmetic in \(\mathbb F_{p^{k}}\) and application to fast pairing computation
• FPGA and ASIC implementations of the \(\eta _T\) pairing in characteristic three

Cited in

(5)

• RNS arithmetic in \(\mathbb F_{p^{k}}\) and application to fast pairing computation
• High speed flexible pairing cryptoprocessor on FPGA platform
• FPGA implementation of pairings using residue number system and lazy reduction
• Core Based Architecture to Speed Up Optimal Ate Pairing on FPGA Platform
• Low-cost addition-subtraction sequences for the final exponentiation in pairings

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