FPGA and ASIC implementations of the _T pairing in characteristic three
DOI10.1016/J.COMPELECENG.2009.05.001zbMATH Open1192.68235OpenAlexW2116492304MaRDI QIDQ962585FDOQ962585
Authors: Jean-Luc Beuchat, Hiroshi Doi, Kaoru Fujita, Atsuo Inomata, Piseth Ith, Akira Kanaoka, Masayoshi Katouno, Masahiro Mambo, Eiji Okamoto, Takeshi Okamoto, Takaaki Shiga, Masaaki Shirase, Ryuji Soga, Tsuyoshi Takagi, Ananda Vithanage, Hiroyasu Yamamoto 
Publication date: 7 April 2010
Published in: Computers and Electrical Engineering (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/j.compeleceng.2009.05.001
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- Hardware Acceleration of the Tate Pairing in Characteristic Three
- Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
- A Comparison between Hardware Accelerators for the Modified Tate Pairing over $\mathbb{F}_{2^m}$ and $\mathbb{F}_{3^m}$
- Implementing cryptographic pairings on accumulator based smart card architectures
- A Coprocessor for the Final Exponentiation of the η T Pairing in Characteristic Three
- Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
- High speed cryptoprocessor for \(\eta _{T }\) pairing on 128-bit secure supersingular elliptic curves over characteristic two fields
- Efficient pairings and ECC for embedded systems
- Hardware architectures for the Tate pairing over GF\((2^{m})\)
- Hardware implementation of pairings
- Faster pairing coprocessor architecture
- FPGA implementation of pairings using residue number system and lazy reduction
- Compact hardware for computing the Tate pairing over 128-bit-security supersingular curves
- Faster Implementation of η T Pairing over GF(3 m ) Using Minimum Number of Logical Instructions for GF(3)-Addition
- Hydra: an energy-efficient programmable cryptographic coprocessor supporting elliptic-curve pairings over fields of large characteristics
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