Flexible reference trace reduction for VM simulations
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Cited in
(6)- Engineering efficient paging algorithms
- Efficient stack simulation for set-associative virtual address caches with real tags
- {\textsc{FastSlim}}: prefetch-safe trace reduction for I/O cache simulation
- scientific article; zbMATH DE number 2090627 (Why is no real title available?)
- The optimal structure of algorithms for \(\alpha\)-paging
- Outperforming LRU via competitive analysis on parametrized inputs for paging
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