Hardware performance characterization of block cipher structures

DOI10.1007/3-540-36563-X_12MaRDI QIDQ4418535zbMATH OpenFDO

Authors Lu Xiao, Howard M. Heys

Publication date 10 August 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2612/26120176.htm

zbMATH Keywords

Feistel networkshardware complexitymaximum distance separable mappingssecuritysubstitution-permutation networks

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10) Data encryption (aspects in computer science) (68P25) Cryptography (94A60)

Recommendations

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Cited in

(7)

• The block cipher Hierocrypt
• Compact Implementation and Performance Evaluation of Block Ciphers in ATtiny Devices
• scientific article; zbMATH DE number 6719508 (Why is no real title available?)
• Evaluation of the maximum performance of block encryption algorithms
• Hardware design and analysis of block cipher components
• On the performance of one perspective LSX-based block cipher
• FOAM: searching for hardware-optimal SPN structures and components with a fair comparison

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