High-Speed Binary-to-Decimal Conversion

DOI10.1109/TC.1968.226913MaRDI QIDQ5537013zbMATH OpenFDO

Authors M. S. Schmookler

Publication date 1968

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1968.226913

zbMATH Keywords

numerical analysis

Cited in

(1)

• Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers

This page was built for publication: High-Speed Binary-to-Decimal Conversion

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5537013)