High-Speed Pipelined Hardware Architecture for Galois Counter Mode
From MaRDI portal
Recommendations
- Progress in Cryptology - INDOCRYPT 2004
- The Security and Performance of “GCM” when Short Multiplications Are Used Instead
- Efficient implementation of the Galois counter mode using a carry-less multiplier and a fast reduction algorithm
- Implementing GCM on ARMv8
- Faster and Timing-Attack Resistant AES-GCM
This page was built for publication: High-Speed Pipelined Hardware Architecture for Galois Counter Mode
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3507871)