High speed 4-symbol arithmetic encoder architecture for embedded zero tree-based compression

DOI10.1023/A:1022123829466MaRDI QIDQ1405490zbMATH OpenOpenAlexFDO

Authors Roberto R. Osorio, Bart Vanhoof

Publication date 25 August 2003

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1022123829466

zbMATH Keywords

arithmetic codingentropy coding

Mathematics Subject Classification ID

Coding and information theory (compaction, compression, models of communication, encoding schemes, etc.) (aspects in computer science) (68P30)

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Cited in

(2)

• High-speed and low-power IP for embedded block coding with optimized truncation (EBCOT) sub-block in JPEG2000 system implementation
• scientific article; zbMATH DE number 1844687 (Why is no real title available?)

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