FPGA-based modelling unit for high speed lossless arithmetic coding

DOI10.1007/3-540-44687-7_71MaRDI QIDQ4786196zbMATH OpenFDO

Authors Riad Stefo, Jóse Núñez, Claudia Feregrino, Sudipta Mahapatra, Simon B. Jones

Publication date 12 December 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2147/21470643

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computing methodologies and applications (68U99)

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(1)

• CAVLC coding algorithm and FPGA realization of high-speed entropy encoder

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