Highly parallel implementation of sub-pixel interpolation for AVS HDTV decoder

DOI10.1631/JZUS.A0820112MaRDI QIDQ1045526zbMATH OpenFDO

Authors Wan-Yi Li, Lu Yu

Publication date 15 December 2009

Published in Journal of Zhejiang University. Science A (Search for Journal in Brave)

zbMATH Keywords

interpolationVLSI architectureAVS HDTV

Mathematics Subject Classification ID

Image processing (compression, reconstruction, etc.) in information and communication theory (94A08) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cited in

(1)

• An efficient architecture of extended linear interpolation for image processing

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