Intermediate representations for design automation of multiprocessor DSP systems

DOI10.1023/A:1020307222052MaRDI QIDQ1857127zbMATH OpenOpenAlexFDO

Authors Neal Bambha, Vida Kianzad, Mukul Khandelia, Shuvra S. Bhattacharyya

Publication date 17 February 2003

Published in Design Automation for Embedded Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1020307222052

zbMATH Keywords

Dataflow graphsdigital signal processingembedded systemsinterprocessor communicationself-timed scheduling

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) General topics in the theory of software (68N01) Computing methodologies and applications (68U99)

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(2)

• Resynchronization for multiprocessor DSP systems
• Self-timed scheduling analysis for real-time applications

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