Interprocedural compiler optimization for partial run-time reconfiguration
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Recommendations
- Optimization of dynamic hardware reconfigurations
- Dynamic reconfiguration architectures for multi-context FPGAs
- Development of a run-time reconfiguration system with low reconfiguration overhead
- Compilation Techniques for Reconfigurable Architectures
- A compiler intermediate representation for reconfigurable fabrics
Cites work
Cited in
(15)- Optimization of dynamic hardware reconfigurations
- Improving software performance with configurable logic
- Interprocedural compiler optimization for partial run-time reconfiguration
- Finding an optimal set of breakpoint locations in a control flow graph
- scientific article; zbMATH DE number 1941132 (Why is no real title available?)
- scientific article; zbMATH DE number 1844653 (Why is no real title available?)
- scientific article; zbMATH DE number 1844645 (Why is no real title available?)
- scientific article; zbMATH DE number 1849104 (Why is no real title available?)
- Low power encoding techniques for dynamically reconfigurable hardware
- Compilation Techniques for Reconfigurable Architectures
- Euro-Par 2004 Parallel Processing
- A new compression based approach for reconfiguration overhead reduction in virtex based RTR systems
- Dynamic scheduling in high-level compilation for adaptive computers.
- Interprocedural analysis and optimization
- scientific article; zbMATH DE number 1844637 (Why is no real title available?)
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