Method of binary log-antilog evaluation in hardware for fast arithmetic- logical units. I (Q1069666)
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scientific article; zbMATH DE number 3936365
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| English | Method of binary log-antilog evaluation in hardware for fast arithmetic- logical units. I |
scientific article; zbMATH DE number 3936365 |
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Method of binary log-antilog evaluation in hardware for fast arithmetic- logical units. I (English)
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1985
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A method is proposed for evaluation of the logarithmic function by linear segmented approximation with minimum arithmetic mean error. Quantitative and statistical error estimates for the evaluation of logarithmic functions by this method are given; time and hardware bounds for the implementation of the proposed method are derived. One of the algorithms that can be used to realize the proposed method is described.
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fast arithmetic-logical units
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logarithmic function
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error estimates
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0.7837924361228943
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0.7471637725830078
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0.7469407916069031
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0.7469407916069031
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0.7391383051872253
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