Layouts with wires of balanced length (Q1091358)

The authors investigate the optimal balanced layouts of the graphs with fixed boundaries in the Euclidean plane. It appears that the main justification for using ''the graph with fixed boundary'' is to model the abstract structure of a circuit together with topological constraints given by the boundary of the chip and fixed i/o-ports. The originality of the present paper lies in the rigorously established existence of a layout which minimizes the maximum distance of any node to its neighbors.