Techniques for efficiently implementing totally self-checking checkers in MOS technology (Q1101080)
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scientific article; zbMATH DE number 4045661
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| English | Techniques for efficiently implementing totally self-checking checkers in MOS technology |
scientific article; zbMATH DE number 4045661 |
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Techniques for efficiently implementing totally self-checking checkers in MOS technology (English)
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1987
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This paper presents some new techniques for reducing the transistor count of MOS implementations of totally self-checking (TSC) checkers. The techniques are (1) transfer of fanouts, (2) removal of inverters and (3) use of multi-level realizations of functions. These techniques also increase the speed of the circuit and may reduce the number of required tests. Their effectiveness has been demonstrated by applying them to m- out-of-n and Berger code checkers. Impressiive reductions of up to 90 \% in the transistor count in some cases have been obtained for the MOS implementation of these checkers. This directly translates into saving of ship area.
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reducing the transistor count of MOS implementations of totally self- checking (TSC) checkers
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m-out-of-n and Berger code checkers
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0.814357340335846
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0.7701398730278015
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0.7684873342514038
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0.7664597630500793
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0.7579820156097412
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