Implementation and performance of a binary lattice gas algorithm on parallel processor systems (Q1112683)
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| Language | Label | Description | Also known as |
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| English | Implementation and performance of a binary lattice gas algorithm on parallel processor systems |
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Implementation and performance of a binary lattice gas algorithm on parallel processor systems (English)
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1989
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We study the performance of a lattice gas binary algorithm on a ``real arithmetic'' machine, a 32 processor INTEL iPSC hypercube. The implementation is based on so-called multi-spin coding techniques. From the measured performance we extrapolate to larger and more powerful parallel systems. Comparisons are made with ``bit'' machines, such as the parallel connection machine.
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lattice gas binary algorithm
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``real arithmetic'' machine
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32 processor INTEL iPSC hypercube
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multi-spin coding techniques
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