An integrated approach to routing and via minimization (Q1183405)

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An integrated approach to routing and via minimization
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    An integrated approach to routing and via minimization (English)
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    28 June 1992
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    We propose that Steiner points can be mapped on to vias in a layout, and by identifying certain properties of optimal Steiner trees, we can minimize the number of vias used. Another important contribution of this communication is the identification of the fact that whenever an interconnection wire takes a bend, it changes its layer, implying that a via needs to be placed at that point. On the Steiner tree, these bends, or corner points, can also be minimized by techniques similar to the ones used for minimizing the number of Steiner points.
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    VLSI routing
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    rectilinear Steiner trees
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    via minimization
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