Getting more phase margin and performance out of PID controllers (Q1307130)
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scientific article; zbMATH DE number 1353727
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| English | Getting more phase margin and performance out of PID controllers |
scientific article; zbMATH DE number 1353727 |
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Getting more phase margin and performance out of PID controllers (English)
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27 October 1999
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PID controller design is investigated for first-order plus lag processes. Gain and phase margins are found for controllers that optimize standard performance indices (ISE, IAE, IATE) as the ratio of dead time to time constant of the process is varied. Examples examine (by simulation) applications to processes with models that are not considered in the body of the paper.
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delay
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gain and phase margins
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PID controller design
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0.8081521987915039
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0.7825663089752197
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0.7715463638305664
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0.7609659433364868
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0.7576144933700562
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