Gate elimination: circuit size lower bounds and \#SAT upper bounds (Q1704573)
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scientific article; zbMATH DE number 6848999
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
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| English | Gate elimination: circuit size lower bounds and \#SAT upper bounds |
scientific article; zbMATH DE number 6848999 |
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Gate elimination: circuit size lower bounds and \#SAT upper bounds (English)
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12 March 2018
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circuit complexity
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lower bounds
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exponential time algorithms
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satisfiability
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0.9789345860481262
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0.8264631032943726
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0.8216400742530823
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0.8108144998550415
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0.808893620967865
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