Mapping matrix multiplication algorithm onto fault-tolerant systolic array (Q1767936)
From MaRDI portal
 | This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Mapping matrix multiplication algorithm onto fault-tolerant systolic array |
scientific article; zbMATH DE number 2142461
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Mapping matrix multiplication algorithm onto fault-tolerant systolic array |
scientific article; zbMATH DE number 2142461 |
Statements
Mapping matrix multiplication algorithm onto fault-tolerant systolic array (English)
0 references
8 March 2005
0 references
Matrix multiplication
0 references
Fault-tolerance
0 references
Systolic arrays
0 references
Numerical examples
0 references
VLSI/WSI algorithms
0 references
0.9667276
0 references
0.94473493
0 references
0.9302028
0 references
0.92771715
0 references
