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scientific article; zbMATH DE number 1904861
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scientific article; zbMATH DE number 1904861 |
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5 May 2003
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fault-tolerant processor
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VLSI technology
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0.94134367
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0.9401064
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0.93762076
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0.92183775
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0.91148186
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0.9024525
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0.89759696
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0.89470863
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The authors present a systematic design methodology that maps a matrix-vector multiplication algorithm to a fault-tolerant processor time optimal systolic array. Their procedure for obtaining a fault-tolerant space-time optimal \(1D\) systolic arrays is an improved version of the data dependence method for designing of systolic arrays combined with an algorithm based fault-tolerant technique. By this technique a single transient/permanent hardware faults in \(1D\) systolic arrays for a matrix-vector multiplication can be detected and corrected. For the entire collection see [Zbl 0872.00028].
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