AOP arithmetic architectures over GF(2\(^m\)) (Q1888264)

This paper presents bit-serial AOP (all one polynomial-AOP) arithmetic architectures over GF\((2^m)\). The proposed architectures have certain advantages related to circuit complexity over some previous architectures. Using a modular multiplier (inner producting-IM-LSB- first exponentiation, MSB-first exponentiation, AB-multiplier)/squarer (squaring circuit -SM-multiplication and squaring-ISM) for the circuit of Altera's MAX+Plus II programs for performing exponentiation, inversion and division, we can implement cryptosystems with low hardware complexity. Using these it is easy to implement VLSI hardware and IC cards of Altera Max+PLUS II SW programs which have a simple architecture.