The block regularised parameter estimator and its parallelisation (Q1899597)

A new block regularised parameter estimator that is compatible with the requirements for implementation on a systolic architecture is presented. The array provides either the prediction error or the filtration error. It is shown that the processor utilisation of the proposed architecture is close to 100\%, that there are no global connections, and that data take only one direction in any given link. The proposed parameter estimator offers significant potential for adaptive control applications, particularly in the real-time domain.