Static consistency checking for Verilog wire interconnects (Q1929355)
From MaRDI portal
!
This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:
scientific article; zbMATH DE number 6122895
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Static consistency checking for Verilog wire interconnects |
scientific article; zbMATH DE number 6122895 |
Statements
Static consistency checking for Verilog wire interconnects (English)
0 references
8 January 2013
0 references
Verilog elaboration
0 references
static array bounds checking
0 references
Verilog wire width consistency
0 references
dead code elimination
0 references
dependent types
0 references
0.6364938616752625
0 references
0.6307687163352966
0 references
0.6217318177223206
0 references
0.6156501770019531
0 references