Static consistency checking for Verilog wire interconnects

DOI10.1007/S10990-011-9072-1MaRDI QIDQ1929355zbMATH OpenOpenAlexFDO

Authors Yanyan Li

Publication date 8 January 2013

Published in Higher-Order and Symbolic Computation (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10990-011-9072-1

zbMATH Keywords

dependent typesVerilog elaborationdead code eliminationstatic array bounds checkingVerilog wire width consistency

Mathematics Subject Classification ID

Theory of programming languages (68N15) Logic programming (68N17)

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Cites work

• scientific article; zbMATH DE number 2238212 (Why is no real title available?)
• A partial evaluator for the untyped lambda-calculus
• Two-level semantics and code generation

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