Designing of parity preserving reversible Vedic multiplier (Q2239697)
From MaRDI portal
| This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use this page instead for the normal view: Designing of parity preserving reversible Vedic multiplier |
scientific article; zbMATH DE number 7420983
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
||
| English | Designing of parity preserving reversible Vedic multiplier |
scientific article; zbMATH DE number 7420983 |
Statements
Designing of parity preserving reversible vedic multiplier (English)
0 references
5 November 2021
0 references
multiplier circuits
0 references
parity preserving
0 references
vedic multiplier
0 references
reversible logic
0 references
reversible computations
0 references
0.8653098940849304
0 references
0.8518216013908386
0 references
0.8246352672576904
0 references
0.7906478643417358
0 references
0.7884019613265991
0 references