Designing of parity preserving reversible Vedic multiplier
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Publication:2239697
DOI10.1007/S10773-021-04903-ZOpenAlexW3193603097MaRDI QIDQ2239697FDOQ2239697
Authors: Meysam Rashno, Majid Haghparast, Mohammad Mosleh 
Publication date: 5 November 2021
Published in: International Journal of Theoretical Physics (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10773-021-04903-z
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Cites Work
- Conservative logic
- Irreversibility and Heat Generation in the Computing Process
- Logical Reversibility of Computation
- Binary-decision-diagram-based decomposition of Boolean functions into reversible logic elements
- Effective designs of reversible Vedic multiplier
- On universality of general reversible multiple-valued logic gates
Cited In (10)
- Design of quantum cost efficient reversible multiplier using Reed-Muller expressions
- Effective designs of reversible Vedic multiplier
- Optimized parity preserving quantum reversible full adder/subtractor
- Novel parity-preserving designs of reversible 4-bit comparator
- A new design of a low-power reversible vedic multiplier
- An efficient design for reversible Wallace unsigned multiplier
- Novel reversible fault tolerant error coding and detection circuits
- Novel designs of nanometric parity preserving reversible compressor
- Efficient circuit design of reversible square
- On design of parity preserving reversible adder circuits
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