Designing of parity preserving reversible Vedic multiplier

DOI10.1007/S10773-021-04903-ZMaRDI QIDQ2239697zbMATH OpenOpenAlexFDO

Authors Meysam Rashno, Majid Haghparast, Mohammad Mosleh

Publication date 5 November 2021

Published in International Journal of Theoretical Physics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10773-021-04903-z

zbMATH Keywords

multiplier circuitsparity preservingreversible computationsreversible logicvedic multiplier

Mathematics Subject Classification ID

Computer system organization (68Mxx) Theory of computing (68Qxx) Circuits, networks (94Cxx)

Recommendations

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Cites work

• Binary-decision-diagram-based decomposition of Boolean functions into reversible logic elements
• Conservative logic
• Effective designs of reversible Vedic multiplier
• Irreversibility and Heat Generation in the Computing Process
• Logical Reversibility of Computation
• On universality of general reversible multiple-valued logic gates

Cited in

(10)

• Design of quantum cost efficient reversible multiplier using Reed-Muller expressions
• Effective designs of reversible Vedic multiplier
• On design of parity preserving reversible adder circuits
• An efficient design for reversible Wallace unsigned multiplier
• Optimized parity preserving quantum reversible full adder/subtractor
• Novel reversible fault tolerant error coding and detection circuits
• Novel parity-preserving designs of reversible 4-bit comparator
• Novel designs of nanometric parity preserving reversible compressor
• A new design of a low-power reversible vedic multiplier
• Efficient circuit design of reversible square

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