NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS

DOI10.1142/S0219749911007447zbMath1219.81076MaRDI QIDQ3015432

Keivan Navi, Majid Haghparast

Publication date: 13 July 2011

Published in: International Journal of Quantum Information (Search for Journal in Brave)

zbMATH Keywords

cyclic codeHamming codefault tolerancequantum computationnanotechnologylow power designreversible logic designparity-preserving reversible circuits

Mathematics Subject Classification ID

Quantum computation (81P68) Cyclic codes (94B15) Statistical mechanics of nanostructures and nanoparticles (82D80) Quantum coding (general) (81P70)

Related Items (4)

Optimization approaches for designing quantum reversible arithmetic logic unit ⋮ On design of parity preserving reversible adder circuits ⋮ Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate ⋮ Novel qutrit circuit design for multiplexer, de-multiplexer, and decoder

Cites Work

• Unnamed Item
• Conservative logic
• MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT
• Irreversibility and Heat Generation in the Computing Process
• Fault-Tolerant Design
• Logical Reversibility of Computation

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