Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

DOI10.1142/S0219749918500168zbMATH Open1396.81070MaRDI QIDQ4584406FDOQ4584406

Authors: Heranmoy Maity, Arindam Biswas, A. K. Bhattacharjee, Anita Pal 

Publication date: 3 September 2018

Published in: International Journal of Quantum Information (Search for Journal in Brave)

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zbMATH Keywords

quantum costshift registergarbage outputsreversible logic gate

Mathematics Subject Classification ID

Quantum computation (81P68) Mathematical problems of computer architecture (68M07)

Cites Work

• Novel reversible fault tolerant error coding and detection circuits

Cited In (3)

• Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate
• Title not available (Why is that?)
• Optimized 4-bit quantum reversible arithmetic logic unit

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