Quantum cost optimized design of 4-bit reversible universal shift register using reduced number of logic gate

DOI10.1142/S0219749918500168MaRDI QIDQ4584406zbMATH OpenFDO

Authors Heranmoy Maity, Arindam Biswas, A. K. Bhattacharjee, Anita Pal

Publication date 3 September 2018

Published in International Journal of Quantum Information (Search for Journal in Brave)

zbMATH Keywords

quantum costshift registergarbage outputsreversible logic gate

Mathematics Subject Classification ID

Quantum computation (81P68) Mathematical problems of computer architecture (68M07)

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Cites work

• Novel reversible fault tolerant error coding and detection circuits

Cited in

(3)

• Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate
• scientific article; zbMATH DE number 5244194 (Why is no real title available?)
• Optimized 4-bit quantum reversible arithmetic logic unit

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