On design of parity preserving reversible adder circuits

DOI10.1007/s10773-016-3133-5zbMath1371.81080OpenAlexW2513003291MaRDI QIDQ2400197

Majid Haghparast, Ali Bolhassani

Publication date: 28 August 2017

Published in: International Journal of Theoretical Physics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10773-016-3133-5

zbMATH Keywords

theoretical physicsfull addercompressorBCD adderbinary to BCD converterparity preserving reversible blocksquantum reversible logic gates

Mathematics Subject Classification ID

Quantum computation (81P68) Quantum algorithms and complexity in the theory of computing (68Q12)

Related Items

Novel quaternary quantum decoder, multiplexer and demultiplexer circuits

Cites Work

• Unnamed Item
• Unnamed Item
• Unnamed Item
• Optimization approaches for designing quantum reversible arithmetic logic unit
• Novel designs of nanometric parity preserving reversible compressor
• On figures of merit in reversible and quantum logic designs
• Conservative logic
• Experimental quantum cryptography.
• NOVEL REVERSIBLE FAULT TOLERANT ERROR CODING AND DETECTION CIRCUITS
• Quantum Computation and Quantum Information
• MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT
• Irreversibility and Heat Generation in the Computing Process
• A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
• Logical Reversibility of Computation