A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach

DOI10.1109/12.485568MaRDI QIDQ4420928zbMATH OpenOpenAlexFDO

Authors Vojin G. Oklobdzija, David Villeger, Simon S. Liu

Publication date 2 November 2003

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.485568

zbMATH Keywords

Dadda's counterVLSI arithmeticWallace tree

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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• Formal Methods in Computer-Aided Design
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