High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

DOI10.1109/TC.1985.1676634MaRDI QIDQ3680755zbMATH OpenFDO

Authors Naofumi Takagi, Hiroto Yasuura, S. Yajima

Publication date 1985

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1985.1676634

zbMATH Keywords

arithmetic operationsbinary integer multiplicationcarry-propagation-free adderhardware algorithmhigh-speed multiplierredundant binary representationsigned-digit number representation

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Symbolic computation and algebraic computation (68W30)

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• Redundant integer representations and fast exponentiation
• Real-time arithmetic unit
• Redundant arithmetic, algorithms and implementations
• A fast fixed point signed multiplication algorithm
• Algorithms for Iterative Array Multiplication
• A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
• Beyond-Binary Arithmetic: Algorithms and VLSI Implementations.
• Fast Radix-10 Multiplication Using Redundant BCD Codes
• On the distribution of runs of ones in binary strings

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