Redundant arithmetic, algorithms and implementations

DOI10.1016/S0167-9260(00)00015-8MaRDI QIDQ2734606zbMATH OpenOpenAlexWikidataFDO

Authors Andrés Felipe Gonzalez, P. Mazumder

Publication date 20 August 2001

Published in Integration. The VLSI Journal (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/s0167-9260(00)00015-8

zbMATH Keywords

current-mode logicmultiple-valued logicquantum electronic circuitsredundant binary logicredundant number systems

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Nonnumerical algorithms (68W05)

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Cited in

(9)

• Further reducing the redundancy of a notation over a minimally redundant digit set
• A signed binary addition circuit based on an alternative class of addition tables
• High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
• Logic Design of a Fast Circuit for Iterative Additions in Redundant Hybrid Number Systems
• scientific article; zbMATH DE number 1264215 (Why is no real title available?)
• scientific article; zbMATH DE number 1045474 (Why is no real title available?)
• Beyond-Binary Arithmetic: Algorithms and VLSI Implementations.
• Modified Redundant Representation for Designing Arithmetic Circuits with Small Complexity
• Design of multiple-valued arithmetic circuits using counter tree diagrams

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