The delay of circuits whose inputs have specified arrival times
From MaRDI portal
Publication:2370422
DOI10.1016/j.dam.2006.10.013zbMath1120.68012MaRDI QIDQ2370422
Dieter Rautenbach, Christian Szegedy, Jürgen Werber
Publication date: 26 June 2007
Published in: Discrete Applied Mathematics (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1016/j.dam.2006.10.013
VLSI design; size; depth; circuit; static timing analysis; computer arithmetic; straight-line program; prefix problem
68W35: Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.)
68M07: Mathematical problems of computer architecture
Related Items
Fast prefix adders for non-uniform input arrival times, Delay optimization of linear depth Boolean circuits with prescribed input arrival times, On the cost of optimal alphabetic code trees with unequal letter costs
Cites Work
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Unnamed Item
- Delay optimization of linear depth Boolean circuits with prescribed input arrival times
- Fast multiplication of large numbers
- Circuit complexity
- Bounding Fan-out in Logical Networks
- Parallel Prefix Computation
- Efficient Parallel Evaluation of Boolean Expressions
- Restructuring of Arithmetic Expressions For Parallel Evaluation
- Reduction of Depth of Boolean Networks with a Fan-In Constraint
- The Parallel Evaluation of General Arithmetic Expressions
- A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
- On the Time Required to Perform Addition
- On the Addition of Binary Numbers
- The Parallel Evaluation of Arithmetic Expressions Without Division
- Majority Gate Networks