The delay of circuits whose inputs have specified arrival times

DOI10.1016/j.dam.2006.10.013zbMath1120.68012OpenAlexW2032771012MaRDI QIDQ2370422

Christian Szegedy, Dieter Rautenbach, Jürgen Werber

Publication date: 26 June 2007

Published in: Discrete Applied Mathematics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.dam.2006.10.013

zbMATH Keywords

VLSI designsizedepthcircuitstatic timing analysiscomputer arithmeticstraight-line programprefix problem

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)

Related Items (4)

Delay optimization of linear depth Boolean circuits with prescribed input arrival times ⋮ Fast prefix adders for non-uniform input arrival times ⋮ On the cost of optimal alphabetic code trees with unequal letter costs ⋮ Constructing depth-optimum circuits for adders and \textsc{And}-\textsc{Or} paths

Cites Work

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• A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach
• On the Time Required to Perform Addition
• On the Addition of Binary Numbers
• The Parallel Evaluation of Arithmetic Expressions Without Division
• Majority Gate Networks

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