Fast prefix adders for non-uniform input arrival times

DOI10.1007/s00453-015-0067-xzbMath1403.68082arXiv1411.2917OpenAlexW2167757808MaRDI QIDQ513308

Sophie Spirkl, Stephan Held

Publication date: 6 March 2017

Published in: Algorithmica (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/1411.2917

zbMATH Keywords

delayadditioncircuitnon-uniform input arrival timesparallel prefix problemprefix adder

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Numerical algorithms for computer arithmetic, etc. (65Y04)

Related Items (1)

Constructing depth-optimum circuits for adders and \textsc{And}-\textsc{Or} paths

Cites Work

• Delay optimization of linear depth Boolean circuits with prescribed input arrival times
• Faster optimal parallel prefix sums and list ranking
• The delay of circuits whose inputs have specified arrival times
• On the cost of optimal alphabetic code trees with unequal letter costs
• Parallel Prefix Computation
• A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations

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