Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero

DOI10.1109/TC.2007.70750MaRDI QIDQ4564236zbMATH OpenOpenAlexFDO

Authors Riyaz A. Patel, Mohammed Benaissa, S. Boussakta

Publication date 12 June 2018

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2007.70750

Mathematics Subject Classification ID

Parallel numerical computation (65Y05) Mathematical problems of computer architecture (68M07) Numerical algorithms for computer arithmetic, etc. (65Y04)

Cited in

(4)

• Design of reverse converters for a new flexible RNS five-moduli set \(\{ 2^k, 2^n-1, 2^n+1, 2^{n+1}-1, 2^{n-1}-1 \}\) (\(n\) even)
• Symmetric encryption algorithms in a polynomial residue number system
• \(k\)-block parallel addition versus 1-block parallel addition in non-standard numeration systems
• Fast prefix adders for non-uniform input arrival times

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