Constructing depth-optimum circuits for adders and \textsc{And}-\textsc{Or} paths

DOI10.1016/J.DAM.2021.12.007MaRDI QIDQ2074348zbMATH OpenOpenAlexFDO

Authors Ulrich Brenner, Anna Silvanus, Jannik Silvanus

Publication date 9 February 2022

Published in Discrete Applied Mathematics (Search for Journal in Brave)

Full work available at URL https://arxiv.org/abs/2012.05550

zbMATH Keywords

adder circuitsand-or pathsdepth optimization

Mathematics Subject Classification ID

Theory of computing (68Qxx) Circuits, networks (94Cxx) Boolean algebras (Boolean rings) (06Exx)

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Cites work

• scientific article; zbMATH DE number 5852793 (Why is no real title available?)
• scientific article; zbMATH DE number 6004899 (Why is no real title available?)
• scientific article; zbMATH DE number 4012495 (Why is no real title available?)
• scientific article; zbMATH DE number 176877 (Why is no real title available?)
• scientific article; zbMATH DE number 1033441 (Why is no real title available?)
• scientific article; zbMATH DE number 2024859 (Why is no real title available?)
• scientific article; zbMATH DE number 3301887 (Why is no real title available?)
• A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
• Binary adder circuits of asymptotically minimum depth, linear size, and fan-out two
• Delay optimization of linear depth Boolean circuits with prescribed input arrival times
• Fast prefix adders for non-uniform input arrival times
• Faster carry bit computation for adder circuits with prescribed arrival times
• Logic and discrete mathematics. A concise introduction
• Monotone Circuits for Connectivity Require Super-Logarithmic Depth
• On the Addition of Binary Numbers
• Parallel Prefix Computation
• Sharpening an upper bound on the adder and comparator depths
• Size-depth tradeoff in monotone Boolean formulae
• Size-depth tradeoff in non-monotone Boolean formulae
• The delay of circuits whose inputs have specified arrival times

Describes a project that uses

Uses Software

• OEIS
• JBool

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