Faster linear-size \textsc{and}-\textsc{or} path and adder circuits
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Publication:7347254
Cites work
- A Method for the Construction of Minimum-Redundancy Codes
- A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
- A Regular Layout for Parallel Adders
- Binary adder circuits of asymptotically minimum depth, linear size, and fan-out two
- Combinatorial Merging
- Constructing depth-optimum circuits for adders and \textsc{And}-\textsc{Or} paths
- Delay optimization of linear depth Boolean circuits with prescribed input arrival times
- Fast prefix adders for non-uniform input arrival times
- Faster carry bit computation for adder circuits with prescribed arrival times
- scientific article; zbMATH DE number 5852793 (Why is no real title available?)
- scientific article; zbMATH DE number 6004896 (Why is no real title available?)
- scientific article; zbMATH DE number 4012495 (Why is no real title available?)
- scientific article; zbMATH DE number 3558968 (Why is no real title available?)
- scientific article; zbMATH DE number 3214539 (Why is no real title available?)
- scientific article; zbMATH DE number 3301887 (Why is no real title available?)
- On the Addition of Binary Numbers
- On the Time Required to Perform Addition
- Parallel Prefix Computation
- Sharpening an upper bound on the adder and comparator depths
- Size-depth tradeoff in monotone Boolean formulae
- The delay of circuits whose inputs have specified arrival times
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