A Regular Layout for Parallel Adders
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area-time complexitycarry lookaheadcircuit designcombinational logicmodels of computationparallel additionparallel polynomial evaluationprefix computationVLSI architecture
Cited in
(25)- An easily testable optimal-time VLSI-multiplier
- Communication-efficient parallel algorithms for distributed random-access machines
- The complexity of a VLSI adder
- Computations over finite monoids and their test complexity
- Mod \(m\) arithmetic in binary systems
- Non-associative parallel prefix computation
- Parallel prefix computation with few processors
- A fully parallel algorithm for residue to binary conversion
- A chained-matrices approach for parallel computation of continued fractions and its applications
- Parallel evaluation of arithmetic circuits
- Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems
- A software interface and hardware design for variable-precision interval arithmetic
- A novel parallel prefix adder for optimized radix-2 FFT processor
- Formal verification of parallel prefix sum and stream compaction algorithms in CUDA
- The applicability of discrete performance estimation methods to VLSI design
- A search for Wilson primes
- Formal proof of integer adders using all-prefix-sums operation
- OPTIMAL PARALLEL PREFIX ON MESH ARCHITECTURES
- Limited width parallel prefix circuits
- Chai-Tea, Cryptographic Hardware Implementations of xTEA
- Formal proof of prefix adders
- Cryptanalysis of algebraic verifiable delay functions
- Symbolic computer algebra for multipliers revisited - demonstrating the significance of order and phase optimization
- On the complexity of fanout-bounded parallel prefix circuits
- Faster linear-size \textsc{and}-\textsc{or} path and adder circuits
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