A Regular Layout for Parallel Adders
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combinational logicprefix computationmodels of computationparallel additioncircuit designarea-time complexityVLSI architectureparallel polynomial evaluationcarry lookahead
Cited in
(24)- On the complexity of fanout-bounded parallel prefix circuits
- Limited width parallel prefix circuits
- Communication-efficient parallel algorithms for distributed random-access machines
- A novel parallel prefix adder for optimized radix-2 FFT processor
- Formal verification of parallel prefix sum and stream compaction algorithms in CUDA
- A search for Wilson primes
- A software interface and hardware design for variable-precision interval arithmetic
- The applicability of discrete performance estimation methods to VLSI design
- Parallel algorithms for addition and multiplication on processor arrays with reconfigurable bus systems
- Formal proof of prefix adders
- Symbolic computer algebra for multipliers revisited - demonstrating the significance of order and phase optimization
- A fully parallel algorithm for residue to binary conversion
- OPTIMAL PARALLEL PREFIX ON MESH ARCHITECTURES
- A chained-matrices approach for parallel computation of continued fractions and its applications
- Mod \(m\) arithmetic in binary systems
- Computations over finite monoids and their test complexity
- Formal proof of integer adders using all-prefix-sums operation
- Cryptanalysis of algebraic verifiable delay functions
- Non-associative parallel prefix computation
- The complexity of a VLSI adder
- Parallel prefix computation with few processors
- Chai-Tea, Cryptographic Hardware Implementations of xTEA
- Parallel evaluation of arithmetic circuits
- An easily testable optimal-time VLSI-multiplier
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