The complexity of a VLSI adder

DOI10.1016/0020-0190(80)90010-1MaRDI QIDQ1146001zbMATH OpenOpenAlexFDO

Authors Robert B. jun. Johnson

Publication date 1980

Published in Information Processing Letters (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0020-0190(80)90010-1

zbMATH Keywords

area-time complexitybinary additionVLSI adder

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25)

Cites work

• A Regular Layout for Parallel Adders
• The Area-Time Complexity of Binary Multiplication

Cited in

(4)

• On the VLSI complexity of some arithmetic and numerical problems
• Area-time lower-bound techniques with applications to sorting
• Optimal tradeoffs for addition on systolic arrays
• A VLSI fast solver for tridiagonal linear systems

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