Multilevel reverse-carry addition: Single and dual adders

DOI10.1023/A:1021141818191MaRDI QIDQ1405460zbMATH OpenOpenAlexFDO

Authors Javier D. Bruguera, Tomas Lang

Publication date 25 August 2003

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/a:1021141818191

zbMATH Keywords

computer arithmeticdual addersmost-significant-carry detectionprefix addersVLSI design

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

Recommendations

• scientific article; zbMATH DE number 4057452
• A Way to Build Efficient Carry-Skip Adders
• Fast prefix adders for non-uniform input arrival times
• Faster carry bit computation for adder circuits with prescribed arrival times
• Statistical carry lookahead adders

Cited in

(1)

• Shallow circuits and concise formulae for multiple addition and multiplication

This page was built for publication: Multilevel reverse-carry addition: Single and dual adders

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1405460)