Statistical carry lookahead adders

DOI10.1109/12.485572MaRDI QIDQ4420932zbMATH OpenOpenAlexFDO

Authors A. De Gloria, Mauro Olivieri

Publication date 1996

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.485572

zbMATH Keywords

computer arithmeticself-timed systemsVLSI design

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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Cited in

(5)

• Multilevel reverse-carry addition: Single and dual adders
• Computer arithmetic and hardware: ``off the shelf microprocessors versus ``custom hardware
• A Way to Build Efficient Carry-Skip Adders
• Conditional-Sum Early Completion Adder Logic
• FUNCTIONAL PEARL Derivation of a logarithmic time carry lookahead addition circuit

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