Area-time efficient modulo 2/sup n/-1 adder design

DOI10.1109/82.298378MaRDI QIDQ4317362zbMATH OpenOpenAlexFDO

Authors C. Efstathiou, Dimitris Nikolos, J. Kalamatianos

Publication date 31 January 1995

Published in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/82.298378

zbMATH Keywords

carry look-ahead adderscarry look-ahead addition algorithmsendaround carry addersmodulo \(2^ n- 1\) addersVLSI adders

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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Cited in

(8)

• scientific article; zbMATH DE number 3976938 (Why is no real title available?)
• Design of residue generators and multioperand adders modulo 3 built of multioutput threshold circuits
• Statistical carry lookahead adders
• scientific article; zbMATH DE number 2077628 (Why is no real title available?)
• scientific article; zbMATH DE number 2081107 (Why is no real title available?)
• Mathematical analysis of ripple carry adders based on complements
• Design and Implementation of Modified Signed-Digit Adder
• scientific article; zbMATH DE number 5234276 (Why is no real title available?)

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