Design and Implementation of Modified Signed-Digit Adder

DOI10.1109/TC.2012.285MaRDI QIDQ5268197zbMATH OpenOpenAlexFDO

Authors Jun-Jie Peng, Rong Shen, Yi Jin, Yunfu Shen, Sheng Luo

Publication date 20 June 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2012.285

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04)

Recommendations

• An improved maximally redundant signed digit adder
• A Nonspeculative Maximally Redundant Signed Digit Adder
• Diminished-one modulo 2/sup n/+1 adder design
• On Modulo 2ⁿ+1 Adder Design
• A signed binary addition circuit based on an alternative class of addition tables
• Signed digit addition and related operations with threshold logic
• Reviewing High-Radix Signed-Digit Adders
• Area-time efficient modulo 2/sup n/-1 adder design
• Carry-free addition of recoded binary signed-digit numbers

Cited in

(1)

• scientific article; zbMATH DE number 5234276 (Why is no real title available?)

This page was built for publication: Design and Implementation of Modified Signed-Digit Adder

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5268197)