On Modulo 2ⁿ+1 Adder Design

DOI10.1109/TC.2010.261MaRDI QIDQ5277657zbMATH OpenOpenAlexFDO

Authors Haridimos T. Vergos, Giorgos Dimitrakopoulos

Publication date 12 July 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.2010.261

Mathematics Subject Classification ID

Numerical algorithms for computer arithmetic, etc. (65Y04)

Cited in

(4)

• Application of the residue number system to reduce hardware costs of the convolutional neural network implementation
• Area-time efficient modulo 2/sup n/-1 adder design
• scientific article; zbMATH DE number 2077628 (Why is no real title available?)
• Design and Implementation of Modified Signed-Digit Adder

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