Delay optimization of linear depth Boolean circuits with prescribed input arrival times

DOI10.1016/J.JDA.2005.06.006zbMATH Open1130.94338OpenAlexW2025635553MaRDI QIDQ866541FDOQ866541

Authors Dieter Rautenbach, Christian Szegedy, Jürgen Werber

Publication date 14 February 2007

Published in Journal of Discrete Algorithms (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/j.jda.2005.06.006

zbMATH Keywords

delaycircuitdepthVLSI designcomputer arithmeticstraight-line program

Mathematics Subject Classification ID

Recommendations

• The delay of circuits whose inputs have specified arrival times
• Faster carry bit computation for adder circuits with prescribed arrival times
• The fundamental difference between depth and delay
• On the Delay Required to Realize Boolean Functions
• New inequality relations between depth and delay

Cites work

• scientific article; zbMATH DE number 4012495 (Why is no real title available?)
• scientific article; zbMATH DE number 48134 (Why is no real title available?)
• scientific article; zbMATH DE number 1033441 (Why is no real title available?)
• On the Addition of Binary Numbers
• On the Time Required to Perform Addition
• Parallel Prefix Computation
• The delay of circuits whose inputs have specified arrival times

Cited in

(5)

• Faster carry bit computation for adder circuits with prescribed arrival times
• Constructing depth-optimum circuits for adders and \textsc{And}-\textsc{Or} paths
• On the cost of optimal alphabetic code trees with unequal letter costs
• Fast prefix adders for non-uniform input arrival times
• The delay of circuits whose inputs have specified arrival times

This page was built for publication: Delay optimization of linear depth Boolean circuits with prescribed input arrival times

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q866541)