Delay optimization of linear depth Boolean circuits with prescribed input arrival times

DOI10.1016/J.JDA.2005.06.006zbMATH Open1130.94338OpenAlexW2025635553MaRDI QIDQ866541FDOQ866541

Authors: Dieter Rautenbach, Christian Szegedy, Jürgen Werber 

Publication date: 14 February 2007

Published in: Journal of Discrete Algorithms (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/j.jda.2005.06.006

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zbMATH Keywords

delaycircuitdepthVLSI designcomputer arithmeticstraight-line program

Mathematics Subject Classification ID

Cites Work

• Title not available (Why is that?)
• Parallel Prefix Computation
• Title not available (Why is that?)
• The delay of circuits whose inputs have specified arrival times
• On the Addition of Binary Numbers
• Title not available (Why is that?)
• On the Time Required to Perform Addition

Cited In (5)

• Faster carry bit computation for adder circuits with prescribed arrival times
• The delay of circuits whose inputs have specified arrival times
• On the cost of optimal alphabetic code trees with unequal letter costs
• Constructing depth-optimum circuits for adders and \textsc{And}-\textsc{Or} paths
• Fast prefix adders for non-uniform input arrival times

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