Novel parity-preserving designs of reversible 4-bit comparator

DOI10.1007/S10773-013-1904-9MaRDI QIDQ461832zbMATH OpenOpenAlexFDO

Authors Xue-mei Qi, Fu-long Chen, Hong Tao Wang, Yun-xiang Sun, Liang-min Guo

Publication date 15 October 2014

Published in International Journal of Theoretical Physics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s10773-013-1904-9

zbMATH Keywords

simulationFVGB block and CPGB blockparity-preservingreversible comparatorTVG gate and CPG gate

Mathematics Subject Classification ID

Quantum computation (81P68)

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Cites work

• Conservative logic
• Irreversibility and Heat Generation in the Computing Process
• Logical Reversibility of Computation
• On figures of merit in reversible and quantum logic designs
• Optimization approaches for designing a novel 4-bit reversible comparator

Cited in

(7)

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• Novel reversible fault tolerant error coding and detection circuits
• Novel designs of nanometric parity preserving reversible compressor
• Designing parity preserving reversible circuits
• Optimization approaches for designing a novel 4-bit reversible comparator
• Novel designs of quantum reversible counters
• On design of parity preserving reversible adder circuits

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